The invention relates to an integrated semiconductor memory, comprising memory cells which are arranged in a matrix and peripheral circuits for addressing memory cells at least in order to read data from the addressed memory cells. The invention also relates to an integrated signal processor having such a memory.
Within the family concept of an integrated product, preferably product versions having different storage capacities are made available. An increased storage capacity of an integrated memory implies an increased number of memory cells and an increased addressing capacity of the address decoding circuits in the periphery. In that case the surface area of the substrate increases substantially linearly; this usually has far-reaching consequences because it necessitates redesigning.
Expansion of the storage capacity has far-reaching consequences notably when the memory is integrated on a substrate together with a signal processor. Not only the memory, but also the parts of the processor which are arranged around the memory will be "shifted", so that a completely new lay-out must be made for the integrated processor and the associated memory. Redesigning an integrated product is expensive so that redesigning of a signal processor, necessitated by the expansion of the storage capacity of the memory integrated on the same substrate, is found to be very disadvantageous.